1. Field of the Invention:
The present invention relates to an integrated circuit including therein a programmable circuit such as a programmable logic device (PLD), etc.
2. Description of the Prior Art:
There are conventionally known PLDs (programmable logic devices) and the like which are integrated circuits (IC) capable of being manually programmed by a user to realize a desired circuit. These programmable integrated circuits require that program data corresponding to specifications for logic configurations of the PLDs and circuits, etc. be stored therein. They therefore sometimes include within the logic circuit, a circuit incorporating a non-volatile memory device such as an EPROM (erasable programmable read only memory) or an EEPROM (electrically erasable programmable read only memory). Such an IC is disclosed, for example, in IEEE Journal of Solid-State Circuits, Vol. SC-21, No. 5, October, 1986, pp. 766-773.
There is also another programmable IC which includes a volatile memory device such as an SRAM (static random access memory) for holding program data and transferring the program data from an EPROM or an EEPROM of an external memory IC upon power-up or when the data is needed by volatile memory device.
Such prior programmable ICs, which include non-volatile memory devices, however, suffer from a reduced degree of integration. More specifically, with a non-volatile memory device such as an EPROM integrated in the logic circuit to hold the program data, a high write voltage must be applied to the memory device in order to write program data thereto. It is accordingly necessary to separate the logic circuit and the non-volatile memory device from each other in order to avoid the logic circuit components from being destroyed and latched up during a write separation, which causes the degree of integration of the logic circuit to be lowered. Accordingly, only a few types of programmable logic such as a PLA (programmable logic array), can integrally be incorporated in the logic circuit with the non-volatile memory device. The difficulty described above with respect to the writing is not experienced by a logic device that instead includes a volatile memory device. In this situation, although the logic circuit does not suffer from a reduced degree of integration, it requires an extra external non-volatile memory device which lowers the degree of on-board integration.
To solve such problems, Japanese Laid-Open Patent Publication No. 64-78023 proposes an integrated circuit including therein a non-volatile memory device independent of a volatile memory device. The circuit cannot, however, directly transfer program data from an external source to the volatile memory device, and also requires that the program data be held in the non-volatile memory device. In particular, the circuit is difficult to use for circuit evaluation such as shipping inspection and in-circuit emulation. The circuit is also costly.